(kicad_pcb
	(version 20241229)
	(generator "pcbnew")
	(generator_version "9.0")
	(general
		(thickness 1.6062)
		(legacy_teardrops no)
	)
	(paper "A4")
	(layers
		(0 "F.Cu" signal "SIGU.Cu")
		(4 "In1.Cu" power "GNDU.Cu")
		(6 "In2.Cu" signal "SIGL.Cu")
		(2 "B.Cu" power "GNDL.Cu")
		(13 "F.Paste" user)
		(15 "B.Paste" user)
		(5 "F.SilkS" user "F.Silkscreen")
		(7 "B.SilkS" user "B.Silkscreen")
		(1 "F.Mask" user)
		(3 "B.Mask" user)
		(17 "Dwgs.User" user "User.Drawings")
		(25 "Edge.Cuts" user)
		(27 "Margin" user)
		(31 "F.CrtYd" user "F.Courtyard")
		(29 "B.CrtYd" user "B.Courtyard")
	)
	(setup
		(stackup
			(layer "F.SilkS"
				(type "Top Silk Screen")
				(color "White")
			)
			(layer "F.Paste"
				(type "Top Solder Paste")
			)
			(layer "F.Mask"
				(type "Top Solder Mask")
				(color "Green")
				(thickness 0.01)
			)
			(layer "F.Cu"
				(type "copper")
				(thickness 0.035)
			)
			(layer "dielectric 1"
				(type "prepreg")
				(thickness 0.2104)
				(material "FR4")
				(epsilon_r 4.4)
				(loss_tangent 0.02)
			)
			(layer "In1.Cu"
				(type "copper")
				(thickness 0.0152)
			)
			(layer "dielectric 2"
				(type "core")
				(thickness 1.065)
				(material "FR4")
				(epsilon_r 4.6)
				(loss_tangent 0.02)
			)
			(layer "In2.Cu"
				(type "copper")
				(thickness 0.0152)
			)
			(layer "dielectric 3"
				(type "prepreg")
				(thickness 0.2104)
				(material "FR4")
				(epsilon_r 4.4)
				(loss_tangent 0.02)
			)
			(layer "B.Cu"
				(type "copper")
				(thickness 0.035)
			)
			(layer "B.Mask"
				(type "Bottom Solder Mask")
				(color "Green")
				(thickness 0.01)
			)
			(layer "B.Paste"
				(type "Bottom Solder Paste")
			)
			(layer "B.SilkS"
				(type "Bottom Silk Screen")
				(color "White")
			)
			(copper_finish "ENIG")
			(dielectric_constraints yes)
		)
		(pad_to_mask_clearance 0)
		(allow_soldermask_bridges_in_footprints no)
		(tenting front back)
		(pcbplotparams
			(layerselection 0x00000000_00000000_55555555_5755f5ff)
			(plot_on_all_layers_selection 0x00000000_00000000_00000000_00000000)
			(disableapertmacros no)
			(usegerberextensions no)
			(usegerberattributes yes)
			(usegerberadvancedattributes yes)
			(creategerberjobfile yes)
			(dashed_line_dash_ratio 12.000000)
			(dashed_line_gap_ratio 3.000000)
			(svgprecision 4)
			(plotframeref no)
			(mode 1)
			(useauxorigin no)
			(hpglpennumber 1)
			(hpglpenspeed 20)
			(hpglpendiameter 15.000000)
			(pdf_front_fp_property_popups yes)
			(pdf_back_fp_property_popups yes)
			(pdf_metadata yes)
			(pdf_single_document no)
			(dxfpolygonmode yes)
			(dxfimperialunits yes)
			(dxfusepcbnewfont yes)
			(psnegative no)
			(psa4output no)
			(plot_black_and_white yes)
			(sketchpadsonfab no)
			(plotpadnumbers no)
			(hidednponfab no)
			(sketchdnponfab yes)
			(crossoutdnponfab yes)
			(subtractmaskfromsilk no)
			(outputformat 1)
			(mirror no)
			(drillshape 1)
			(scaleselection 1)
			(outputdirectory "")
		)
	)
	(net 0 "")
	(net 1 "+12V")
	(net 2 "GND1")
	(net 3 "Net-(C2-Pad1)")
	(net 4 "/COMP")
	(net 5 "Net-(J1-Pin_1)")
	(net 6 "Net-(U1-SS)")
	(net 7 "Net-(U1-CS)")
	(net 8 "GND2")
	(net 9 "/VOUT")
	(net 10 "Net-(JP2-B)")
	(net 11 "VDD")
	(net 12 "/PRIMARY-")
	(net 13 "Net-(JP2-A)")
	(net 14 "Net-(D4-Pad2)")
	(net 15 "Net-(D6-A)")
	(net 16 "Net-(GD1-Pad3)")
	(net 17 "/EN_INP")
	(net 18 "Net-(JP1-A)")
	(net 19 "Net-(JP1-B)")
	(net 20 "Net-(Q1-G)")
	(net 21 "/IC_EN")
	(net 22 "Net-(Q2-S)")
	(net 23 "/GATE")
	(net 24 "Net-(U1-RSET)")
	(net 25 "Net-(U1-TC)")
	(net 26 "Net-(U1-FB)")
	(net 27 "Net-(R8-Pad2)")
	(net 28 "unconnected-(RV1-Pad1)")
	(net 29 "unconnected-(U1-NC-Pad2)")
	(net 30 "unconnected-(U1-NC-Pad12)")
	(net 31 "Net-(C5-Pad1)")
	(net 32 "Net-(D8-Pad2)")
	(net 33 "Net-(Q3-D)")
	(net 34 "Net-(D3-Pad1)")
	(net 35 "Net-(Q2-G)")
	(footprint "PCM_JLCPCB:Hole_Tooling_JLCPCB"
		(layer "F.Cu")
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		(at 113 82)
		(property "Reference" "H3"
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		(property "Datasheet" "https://jlcpcb.com/help/article/How-to-add-tooling-holes-for-PCB-assembly-order"
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		(property "Description" "1. Two or three tooling holes should be added on the PCB, they should be placed in opposite corners of the PCB and as far apart from one another as practical. 2. Tooling holes should be 1.152mm(45.4mil) round non-plated holes with 0.148mm solder mask expansion. 3. Tooling holes are only required for PCB assembly orders. 4. Please try to add tooling holes on empty space and keep them away from traces. If there is no enough room, you can add them to the copper area."
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		(path "/3efd87e4-c0f6-4474-8fa3-0dbae2628fac")
		(sheetname "/")
		(sheetfile "Transformer Driver.kicad_sch")
		(attr exclude_from_pos_files exclude_from_bom)
		(fp_text user "${REFERENCE}"
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		(pad "" np_thru_hole circle
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			(drill 1.152)
			(layers "F&B.Cu" "*.Mask")
			(solder_mask_margin 0.148)
			(teardrops
				(best_length_ratio 0.5)
				(max_length 1)
				(best_width_ratio 1)
				(max_width 2)
				(curved_edges no)
				(filter_ratio 0.9)
				(enabled no)
				(allow_two_segments no)
				(prefer_zone_connections no)
			)
			(uuid "46a7d13f-8f83-4167-9950-679753ac9e15")
		)
		(zone
			(net 0)
			(net_name "")
			(layers "F.Cu" "B.Cu" "In1.Cu" "F.SilkS" "In2.Cu" "B.SilkS" "F.Paste"
				"B.Paste" "B.CrtYd" "F.CrtYd"
			)
			(uuid "3fd74f9d-49cb-4d05-8b14-cb147f40e294")
			(hatch edge 0.5)
			(connect_pads
				(clearance 0)
			)
			(min_thickness 0.25)
			(filled_areas_thickness no)
			(keepout
				(tracks not_allowed)
				(vias not_allowed)
				(pads not_allowed)
				(copperpour not_allowed)
				(footprints not_allowed)
			)
			(placement
				(enabled no)
				(sheetname "")
			)
			(fill
				(thermal_gap 0.5)
				(thermal_bridge_width 0.5)
			)
			(polygon
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				)
			)
		)
		(embedded_fonts no)
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	(footprint "PCM_JLCPCB:C_1206"
		(layer "F.Cu")
		(uuid "05fd3336-b6fa-45a7-8743-c0f2fff8b57f")
		(at 105.5 108)
		(descr "Capacitor SMD 1206 (3216 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
		(tags "capacitor")
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